Techniques extracted from the prior art come from the field of sub-micron fabrication technology wherein the dimensional resolution is now comparable to or even smaller than the thicknesses of the thermally grown silicon oxide layers on silicon. Also, the dimensions are now comparable to, or even smaller, than the base widths used for double diffused transistors, i.e. 0.4-1.0 micrometers. From these techniques, the novel structure and method for the NPN lateral transistor with greatly reduced parasitic capacitance and resistances is achieved.